i.MX RT700
NXP Semiconductors
The i.MX RT700 MCU includes five independent functional domains: • Compute • Sense • Common • Digital Signal Processing (DSP) • Media
Application NoteNxp
Multi-Core Application Development on i.MX RT700
Guide for managing memory, cache, boot sequences, and inter-core communication across the five heterogeneous cores of the NXP i.MX RT700 MCU.
Overview
This application note provides a technical overview of multi-core development for the i.MX RT700 crossover MCU. The device integrates five heterogeneous cores: two Arm Cortex-M33 processors, a Cadence Tensilica HiFi4 DSP, a HiFi1 DSP, and a RISC-V EZH-V core. The document details the memory architecture across Compute, Sense, Common, DSP, and Media domains, explaining how RAM arbiters manage access to shared SRAM partitions. It covers cache controller configurations (CACHE64) and Memory Protection Unit (MPU) settings to ensure data coherency and performance optimization. Additionally, it addresses the use of Tightly Coupled Memory (TCM) and bus matrices (M-Bus, P-Bus, and S-Bus) to facilitate efficient inter-core communication and resource allocation.
Use Cases
- Developing multi-core firmware for heterogeneous MCU architectures
- Configuring shared memory and avoiding resource conflicts in i.MX RT700
- Implementing cache-coherent data structures between Arm and DSP cores
- Optimizing inter-processor communication and boot sequences
- Managing SmartDMA tasks using the RISC-V EZH-V core
Topics
i.MX RT700
AN14618
Cortex-M33
HiFi4 DSP
HiFi1 DSP
RISC-V EZH-V
Multi-core architecture
Memory Arbiter
Cache Coherency
SRAM Partitioning
SmartDMA
MPU configuration
Referenced Parts
| i.MX RT700 | NXP Semiconductors | The i.MX RT700 MCU includes five independent functional domains: • Compute • Sense • Common • Digital Signal Processing (DSP) • Media |