MPC107
NXP
MPC107 PCI Bridge/Memory Controller User’s Manual
Design DocumentNxp
NXP MPC107 PCI Bridge/Memory Controller User Manual
User manual for the NXP MPC107 PCI bridge and memory controller, detailing the PowerPC 60x interface, SDRAM controller, DMA engine, and integrated interrupt controller.
Overview
This technical manual provides comprehensive details on the MPC107 PCI bridge and memory controller. The MPC107 serves as an interface between PowerPC 60x processors, SDRAM memory systems, and the PCI bus. Key functional blocks include a high-performance memory interface, a PCI version 2.1 compliant interface with an internal arbiter, a four-channel DMA controller, and an Embedded Programmable Interrupt Controller (EPIC). The document covers signal descriptions, clock generation for the CPU and PCI bus, memory address mapping, I2C interface operations, and power management modes. It also includes information on the Message Unit for Intelligent I/O (I2O) support and detailed configuration register descriptions.
Use Cases
- Developing embedded systems based on PowerPC 60x processors
- Designing PCI bus interfaces for industrial computing
- Implementing SDRAM memory subsystems in embedded designs
- Configuring interrupt management using EPIC
- Designing DMA-driven data transfer systems
Topics
MPC107
NXP
PCI Bridge
Memory Controller
PowerPC 60x
SDRAM Controller
DMA Controller
EPIC
I2C
I2O
Freescale Semiconductor
Referenced Parts
| MPC107 | NXP | MPC107 PCI Bridge/Memory Controller User’s Manual |