MPC823
NXP
MPC823SIU.pdf
Design DocumentNxp
NXP MPC823 and MPC860 SIU Interrupt Controller Technical Overview
A technical guide to the System Interface Unit (SIU) interrupt controller for MPC823 and MPC860 processors, covering register configuration, priorities, and initialization.
Overview
This document provides a detailed technical overview of the System Interface Unit (SIU) interrupt controller for the NXP MPC823 and MPC860 PowerPC processors. It describes the management of eight external interrupt sources (IRQ0-7) and eight internal sources, including the Communication Processor Module (CPM), Periodic Interrupt Timer (PIT), Real-Time Clock (RTC), and Time Base (TB). The guide explains interrupt priority levels, where IRQ0 holds the highest priority, and details the functionality of key registers such as SIPEND for pending interrupts, SIMASK for masking, and SIEL for edge or level sensitivity. It further outlines the interrupt vector table handling at offset 500 hex, the use of the SIVEC register for efficient branch table indexing, and the specific steps required for interrupt initialization and service routine implementation, including context switching and recoverable interrupt state management.
Use Cases
- Configuring hardware interrupt priorities in MPC8xx based embedded systems
- Developing and initializing interrupt service routines for PowerPC architectures
- Managing internal peripheral interrupts from PIT, RTC, and CPM modules
- Implementing low-power wake-up triggers via external IRQ lines
Topics
MPC823
MPC860
SIU
Interrupt Controller
PowerPC
SIPEND
SIMASK
SIVEC
SIEL
CPM
IRQ
Vector Table
Referenced Parts
MPC860
NXP
Motorola Technical Training - MPC860 Course
| MPC823 | NXP | MPC823SIU.pdf |
| MPC860 | NXP | Motorola Technical Training - MPC860 Course |