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Design DocumentNxp

NXP MSC8156E Six Core Digital Signal Processor Reference Manual

Comprehensive reference manual for the NXP MSC8156E six-core StarCore SC3850 DSP, covering architecture, memory systems, security engine, and high-speed communication interfaces.

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Overview

This reference manual provides technical details for the MSC8156E and MSC8154 Digital Signal Processors from NXP (formerly Freescale). The processors utilize six StarCore SC3850 DSP cores and include the Multi Accelerator Platform Engine (MAPLE-B) for baseband processing. The document details the device architecture, including the Chip-Level Arbitration and Switching System (CLASS), internal L1/L2/M3 memory subsystems, and dual DDR-SDRAM controllers. Integrated peripherals covered include Serial RapidIO, PCI Express, the QUICC Engine subsystem for Ethernet and SPI, TDM interfaces, and a dedicated security engine (SEC). It also describes interrupt handling, DMA controllers, boot options, and hardware debugging features.

Use Cases

  • 3G-LTE wireless infrastructure
  • Baseband processing for cellular base stations
  • High-speed data networking and switching
  • Secure communication systems
  • Multi-core DSP application development

Topics

MSC8156E
MSC8154
StarCore SC3850
Digital Signal Processor
MAPLE-B
QUICC Engine
Serial RapidIO
PCI Express
DDR3
Security Engine
DSP

Referenced Parts

MSC8156E

Freescale Semiconductor

MSC8156E Reference Manual Six Core Digital Signal Processor with Security

MSC8154

Freescale Semiconductor

MSC8154 SC3850 DSP Subsystem

0x7

Maxim

BTSZ 0x7 Maximum transfer size is one burst of 64 bytes

0x7

Maxim

BTSZ 0x7 Maximum transfer size is one burst of 64 bytes.

0xFFFFFF

Maxim

0xFFFFFF Maximum Interrupt Report Interval

256-byte

Maxim

• 256-byte maximum payload size (MAX_PAYLOAD_SIZE)

256-byte

Maxim

„ 256-byte maximum payload size (MAX_PAYLOAD_SIZE).

64-Gbyte

Maxim

size may be programmed less than the 64-Gbyte maximum. However, accesses that miss all other windows