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NXP MSC8157 Broadband Wireless Access Six-Core DSP Reference Manual

Reference manual for the MSC8157 six-core StarCore SC3850 DSP, featuring MAPLE-B2 acceleration and high-speed interfaces for broadband wireless infrastructure.

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Overview

This technical reference manual provides a detailed description of the NXP MSC8157 digital signal processor (DSP), designed for high-performance broadband wireless access. The device integrates six StarCore SC3850 cores with the Multi Accelerator Platform Engine (MAPLE-B2) for baseband acceleration. Key subsystems detailed include the Chip-Level Arbitration and Switching System (CLASS) fabric, high-speed serial interfaces (Serial RapidIO, PCI Express, CPRI, and SGMII), a DDR-SDRAM controller, and the QUICC Engine for communication protocol handling. The document covers architectural overviews, memory mapping, clocking, interrupt handling, and peripheral configuration for system hardware and software implementers.

Use Cases

  • Wireless Basestation Baseband Processing
  • LTE and WiMAX Infrastructure
  • High-throughput Wireless Communication Systems
  • Multi-core DSP System Development
  • High-speed Signal Processing Applications

Topics

MSC8157
StarCore SC3850
MAPLE-B2
Digital Signal Processor
Broadband Wireless Access
Serial RapidIO
CPRI
PCI Express
QUICC Engine
DDR Controller

Referenced Parts

MSC8157

NXP

MSC8157 Reference Manual Broadband Wireless Access Six Core DSP

0x0000

Maxim

0x0000 Maximum PDU

0x40

Maxim

0x40 Maximum Transmission Unit

0x7

Maxim

BTSZ 0x7 Maximum transfer size is one burst of 64 bytes

0x7

Maxim

BTSZ 0x7 Maximum transfer size is one burst of 64 bytes.

256-byte

Maxim

• 256-byte maximum payload size (MAX_PAYLOAD_SIZE)

256-byte

Maxim

„ 256-byte maximum payload size (MAX_PAYLOAD_SIZE).

64-Gbyte

Maxim

size may be programmed less than the 64-Gbyte maximum. However, accesses that miss all other windows

NXP MSC8157 Broadband Wireless Access Six-Core DSP Reference Manual | Design Resources