Kinetis-M
NXP Semiconductors
The NXP Kinetis-M power meter reference design is installed on the metering test bench, calibrated using single point calibration technique, and the accuracy of the reference design is verified after the calibration.
Application note for single-point calibration at 0.5 Lagging Power Factor for electronic power meters to optimize production time while maintaining Class 1.0 accuracy.
This application note details a single-point calibration method for electronic power meters, specifically demonstrated using NXP Kinetis-M reference designs. The technique focuses on calibrating at a Power Factor (PF) of 0.5 Lagging to compensate for hardware tolerances and software calculation errors. By targeting the 0.5 L point, which is the most sensitive to phase angle measurement errors, the method ensures measurement accuracy across all quadrants while reducing the time required for production-line testing. The document provides error calculation formulas, automated software flowcharts for coefficient calculation, and instructions for storing gain and phase angle coefficients in non-volatile memory.
Kinetis-M
NXP Semiconductors
The NXP Kinetis-M power meter reference design is installed on the metering test bench, calibrated using single point calibration technique, and the accuracy of the reference design is verified after the calibration.
| Kinetis-M | NXP Semiconductors | The NXP Kinetis-M power meter reference design is installed on the metering test bench, calibrated using single point calibration technique, and the accuracy of the reference design is verified after the calibration. |