Application NoteNxp

SPI/DMA Implementations Using i.MX RT500 (AN14170)

Guidelines for resolving SPI data stalls and Rx FIFO overflows during high-bandwidth DMA traffic on NXP i.MX RT500 and RT600 microcontrollers.

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Overview

This application note details methods to replicate and resolve SPI performance limitations on the i.MX RT500 and RT600 families during high-bandwidth DMA traffic. It describes a scenario where heavy DMA loads lead to Rx FIFO overflows and missing data bytes. The document provides a hardware-based solution utilizing DMA channel chaining and trigger output mechanisms (DMAC0_TRIGOUT_A). By synchronizing Rx and Tx DMA channels through hardware triggers and implementing artificial misalignment in burst transfers, developers can achieve reliable 'back-to-back' SPI transfers without CPU intervention.

Use Cases

High-bandwidth serial data acquisition
Audio digital signal processing
Embedded systems requiring low CPU overhead
High-speed peripheral communication

Topics

i.MX RT500

i.MX RT600

SPI

DMA

Flexcomm

Rx FIFO overflow

channel chaining

DMA trigger

NXP microcontrollers

Referenced Parts

i.MX RT500

NXP Semiconductors

The i.MX RT500 is a family of dual-core microcontrollers for embedded applications featuring an Arm Cortex-M33 CPU combined with a Cadence Xtensa Fusion F1 Audio Digital Signal Processor CPU.

i.MX RT600

NXP Semiconductors

Keywords i.MX RT500, i.MX RT600, SPI

i.MX RT500	NXP Semiconductors	The i.MX RT500 is a family of dual-core microcontrollers for embedded applications featuring an Arm Cortex-M33 CPU combined with a Cadence Xtensa Fusion F1 Audio Digital Signal Processor CPU.
i.MX RT600	NXP Semiconductors	Keywords i.MX RT500, i.MX RT600, SPI