MC9S08QE128
NXP
Launch CodeWarrior and use the wizard to create a project for MC9S08QE128
Application NoteNxp
Understanding Memory Paging in 9S08 Devices
This application note explains memory paging and the Memory Management Unit (MMU) in NXP 9S08 microcontrollers to expand addressing capabilities beyond the standard 64 KB limit.
Overview
This document (AN3730) provides a technical overview of memory paging and the Memory Management Unit (MMU) used in NXP 9S08 microcontrollers with flash memory capacities exceeding 60 KB. It explains how the 16-bit architecture uses the Program Page (PPAGE) register to access additional memory through a 16 KB paging window. The note details the Linear Address Pointer (LAP) and its associated registers (LB, LBP, LWP) for direct access to the full 128 KB memory map. Additionally, it offers guidance on software implementation using CodeWarrior, covering memory model selection (Tiny, Small, and Banked) and the application of near and far compiler directives for code optimization.
Use Cases
- Expanding flash memory access beyond 64 KB in 8-bit microcontroller designs
- Managing large data tables using Linear Address Pointer registers
- Optimizing software performance by placing time-critical functions in local memory versus paged memory
- Configuring memory models and PRM files in CodeWarrior for paged 9S08 derivatives
Topics
NXP
9S08
MC9S08QE128
9S08AW60
9S08AC128
Memory Management Unit
MMU
PPAGE
Memory Paging
Linear Address Pointer
Flash Memory
CodeWarrior
Referenced Parts
9S08AC128
NXP
9S08AC128 data sheet ………………….Freescale Semiconductor
9S08AW60
NXP
Figure 1 shows the 9S08AW60 memory map that has the standard linear memory used in 9S08 devices.
| MC9S08QE128 | NXP | Launch CodeWarrior and use the wizard to create a project for MC9S08QE128 |
| 9S08AC128 | NXP | 9S08AC128 data sheet ………………….Freescale Semiconductor |
| 9S08AW60 | NXP | Figure 1 shows the 9S08AW60 memory map that has the standard linear memory used in 9S08 devices. |