DSP56307

24-bit digital signal processor uses the DSP56300 core family architecture for wireless infrastructure and filtering workloads. The device provides 100 MIPS performance with a 100 MHz internal clock, a 2.5 V core supply, and independent 3.3 V I/O supplies. On-chip resources include 64K of 24-bit RAM, a bootstrap ROM, six-channel DMA, an enhanced filtering coprocessor, HI08 host interface, two ESSI ports, SCI, timers, JTAG, and up to 34 GPIO pins. The available package is a 196-pin plastic ball grid array with a specified junction operating temperature range from -40 °C to +100 °C.