The QUICC communications controller combines a 32-bit CPU32-compatible core with integrated communications peripherals for embedded controller applications. It supports a 0 MHz to 33 MHz static design, up to a 32-bit data bus, and 32 address lines. The device integrates an eight-bank memory controller, four general-purpose timers, two independent DMA channels, and a RISC communications processor module. Serial resources include four SCCs, two SMCs, one SPI port, four baud-rate generators, and support for two TDM channels.
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| Processor core | 32-bit CPU32-compatible core |
| Operating frequency | 0 to 33MHz |
| Data bus width | Up to 32bit |
| Address lines | 32 |
| Memory controller banks | 8 |
| General-purpose timers | Four 16-bit timers or two 32-bit timers |
| Independent DMA channels | 2 |
| Dual-port RAM | 2.5kbytes |
| Serial DMA channels | 14 |
| Baud-rate generators | 4 |
| Serial communications controllers | 4 SCCs |
| Serial management controllers | 2 SMCs |
| SPI ports | 1 |
| TDM channels | 2 |
| Test access port | IEEE 1149.1 |
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These are design resources that include the Freescale Semiconductor MC68MH360
Guidelines for connecting multiple MC145574 (S/T) or MC145572 (U) ISDN transceivers to a QUICC32 (MC68MH360) using QMC protocol and IDL2 TDM bus structures.
