
Synchronous SRAM chip, 72M-bit density, featuring a 4M x 18 configuration with a 20-bit address bus. Offers a maximum access time of 0.45 ns and a maximum clock rate of 450 MHz, utilizing a QDR data rate architecture. This surface-mount component is housed in a 165-pin Fine Pitch Ball Grid Array (FBGA) package with a 1mm pin pitch, operating at a typical supply voltage of 1.8V.
GSI GS8662DT19BD-450 technical specifications.
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