
Synchronous SRAM chip, 72M bit density, featuring a 4M x 18 configuration with a 2-port, pipelined architecture. Delivers a maximum access time of 0.45 ns and supports a maximum clock rate of 200 MHz with QDR data rate architecture. Operates at a typical 1.8V supply voltage, with a range of 1.7V to 1.9V. Encased in a 165-pin Fine Pitch Ball Grid Array (FBGA) package, measuring 17mm x 15mm with a 1mm pin pitch, suitable for surface mounting.
GSI GS8672D18AGE-200 technical specifications.
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