SRAM Chip Async Dual 3.3V 128K-Bit 8K x 16 55ns 84-Pin PLCC T/R
IDT 70V25L55J8 technical specifications.
| Access Time | 55ns |
| Address Bus Width | 26b |
| Package/Case | PLCC |
| Density | 128Kb |
| Interface | Parallel |
| Lead Free | Contains Lead |
| Length | 29.2mm |
| Max Operating Temperature | 70°C |
| Max Supply Voltage | 3.6V |
| Memory Type | RAM, |
| Min Operating Temperature | 0°C |
| Min Supply Voltage | 3V |
| Mount | Surface Mount |
| Number of Ports | 2 |
| Number of Words | 8000 |
| Operating Supply Voltage | 3.3V |
| Packaging | Tape and Reel |
| Radiation Hardening | No |
| RoHS Compliant | No |
| Supply Current | 155mA |
| Sync/Async | Asynchronous |
| Thickness | 3.63mm |
| Width | 29.2mm |
| Word Size | 16b |
| RoHS | Not CompliantNo |
No datasheet is available for this part.
