SRAM Chip Async Dual 5V 8K-Bit 1K x 8 100ns 48-Pin LCC
IDT 7130SA100L48B technical specifications.
| Access Time | 100ns |
| Address Bus Width | 20b |
| Package/Case | LCC |
| Density | 8Kb |
| Interface | Parallel |
| Lead Free | Contains Lead |
| Length | 14.2mm |
| Max Operating Temperature | 125°C |
| Max Supply Voltage | 5.5V |
| Memory Size | 8Kb |
| Memory Type | RAM, , SDR |
| Min Operating Temperature | -55°C |
| Min Supply Voltage | 4.5V |
| Mount | Surface Mount |
| Number of Ports | 2 |
| Number of Words | 1000 |
| Operating Supply Voltage | 5V |
| Package Quantity | 34 |
| Packaging | Rail/Tube |
| Radiation Hardening | No |
| RoHS Compliant | No |
| Supply Current | 190mA |
| Sync/Async | Asynchronous |
| Thickness | 1.78mm |
| Width | 14.2mm |
| Word Size | 8b |
| RoHS | Not CompliantNo |
No datasheet is available for this part.
