512Mbit DDR SDRAM memory chip, organized as 16Mx32, featuring a 32-bit data bus width and a maximum clock rate of 133 MHz. This surface-mount component utilizes a 90-pin WBGA package with a 0.8mm pin pitch and dimensions of 13mm x 8mm x 1mm. Operating at a typical 1.8V supply voltage, it offers a maximum access time of 6ns and includes 4 internal banks.
PackageWBGA
MountingSurface Mount
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Technical Specifications
Integrated Silicon Solution IS43LR32160B-75BL technical specifications.
General
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | WBGA |
| Lead Shape | Ball |
| Pin Count | 90 |
| PCB | 90 |
| Package Length (mm) | 13 |
| Package Width (mm) | 8 |
| Package Height (mm) | 1(Max) |
| Seated Plane Height (mm) | 1.4(Max) |
| Pin Pitch (mm) | 0.8 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Density | 512Mbit |
| Type | DDR SDRAM |
| Organization | 16Mx32 |
| Data Bus Width | 32bit |
| Maximum Clock Rate | 133MHz |
| Number of Internal Banks | 4 |
| Number of Words per Bank | 4M |
| Maximum Access Time | 8|6ns |
| Density in Bits | 536870912bit |
| Address Bus Width | 15bit |
| Maximum Operating Current | 110mA |
| Typical Operating Supply Voltage | 1.8V |
| Max Operating Supply Voltage | 1.95V |
| Min Operating Supply Voltage | 1.7V |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 70°C |
Compliance
| Cage Code | 1J9V2 |
| EU RoHS | Yes |
| HTS Code | 8542320028 |
| Schedule B | 8542320015 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2011/65/EU, 2015/863 |
Datasheet
Integrated Silicon Solution IS43LR32160B-75BL Datasheet
Download the complete datasheet for Integrated Silicon Solution IS43LR32160B-75BL to view detailed technical specifications.
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