Synchronous SRAM chip, 4M-bit density, organized as 256K words by 18 bits. Features a 6.5 ns maximum access time and operates at a maximum clock rate of 133 MHz with SDR data rate architecture. This dual-port memory utilizes a flow-through architecture and is housed in a 119-pin BGA package for surface mounting. Operates from a 3.3V supply voltage with a temperature range of -40°C to 85°C.
PackageBGA
MountingSurface Mount
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Technical Specifications
Integrated Silicon Solution IS61NLF25618A-6.5B2I technical specifications.
General
Basic Package Type
Ball Grid Array
Package Family Name
BGA
Package/Case
BGA
Package Description
Plastic Ball Grid Array
Lead Shape
Ball
Pin Count
119
PCB
119
Package Length (mm)
22.2(Max)
Package Width (mm)
14.2(Max)
Package Height (mm)
1.7(Max)
Seated Plane Height (mm)
2.41(Max)
Pin Pitch (mm)
1.27
Package Material
Plastic
Mounting
Surface Mount
Density
4Mbit
Address Bus Width
18bit
Maximum Access Time
6.5ns
Timing Type
Synchronous
Maximum Clock Rate
133MHz
Data Rate Architecture
SDR
Density in Bits
4194304bit
Maximum Operating Current
180mA
Typical Operating Supply Voltage
3.3V
Number of Bits per Word
18bit
Number of Ports
2
Number of Words
256K
Min Operating Supply Voltage
3.25V
Max Operating Supply Voltage
3.35V
Min Operating Temperature
-40°C
Max Operating Temperature
85°C
Architecture
Flow-Through
Compliance
Cage Code
1J9V2
EU RoHS
No
HTS Code
8542320041
Schedule B
8542320040
ECCN
3A991.b.2.a
Automotive
No
AEC Qualified
No
PPAP
No
Radiation Hardening
No
RoHS Versions
2011/65/EU, 2015/863
Datasheet
Integrated Silicon Solution IS61NLF25618A-6.5B2I Datasheet
Download the complete datasheet for Integrated Silicon Solution IS61NLF25618A-6.5B2I to view detailed technical specifications.
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