Synchronous SRAM chip with 4M-bit density, organized as 128K words by 36 bits. Features a maximum access time of 7.5 ns and a maximum clock rate of 117 MHz with SDR data rate architecture. This surface-mount component utilizes a 100-pin Thin Quad Flat Package (TQFP) with a 0.65mm pin pitch. Operates at a typical supply voltage of 2.5V, with a 17-bit address bus and four ports.
PackageTQFP
MountingSurface Mount
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Technical Specifications
Integrated Silicon Solution IS61NVF12836A-7.5TQ technical specifications.
General
Basic Package Type
Lead-Frame SMT
Package Family Name
QFP
Package/Case
TQFP
Package Description
Thin Quad Flat Package
Lead Shape
Gull-wing
Pin Count
100
PCB
100
Package Length (mm)
20.1(Max)
Package Width (mm)
14.1(Max)
Package Height (mm)
1.45(Max)
Seated Plane Height (mm)
1.6(Max)
Pin Pitch (mm)
0.65
Package Material
Plastic
Mounting
Surface Mount
Jedec
MS-026BHA
Density
4Mbit
Address Bus Width
17bit
Maximum Access Time
7.5ns
Timing Type
Synchronous
Maximum Clock Rate
117MHz
Data Rate Architecture
SDR
Density in Bits
4194304bit
Maximum Operating Current
155mA
Typical Operating Supply Voltage
2.5V
Number of Bits per Word
36bit
Number of Ports
4
Number of Words
128K
Min Operating Supply Voltage
2.45V
Max Operating Supply Voltage
2.55V
Min Operating Temperature
0°C
Max Operating Temperature
70°C
Architecture
Flow-Through
Compliance
Cage Code
1J9V2
EU RoHS
No
HTS Code
8542320041
Schedule B
8542320040
ECCN
3A991.b.2.a
Automotive
No
AEC Qualified
No
PPAP
No
Radiation Hardening
No
RoHS Versions
2011/65/EU, 2015/863
Datasheet
Integrated Silicon Solution IS61NVF12836A-7.5TQ Datasheet
Download the complete datasheet for Integrated Silicon Solution IS61NVF12836A-7.5TQ to view detailed technical specifications.
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