Synchronous SRAM chip, 4M-bit density, 256K x 18 configuration, featuring a 6.5 ns maximum access time and 133 MHz maximum clock rate. This dual-port memory utilizes SDR data rate architecture and a flow-through design. Packaged in a 119-pin plastic Ball Grid Array (BGA) with a 1.27 mm pin pitch, it operates at a typical 2.5V supply voltage.
PackageBGA
MountingSurface Mount
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Technical Specifications
Integrated Silicon Solution IS61NVF25618A-6.5B2 technical specifications.
General
Basic Package Type
Ball Grid Array
Package Family Name
BGA
Package/Case
BGA
Package Description
Plastic Ball Grid Array
Lead Shape
Ball
Pin Count
119
PCB
119
Package Length (mm)
22.2(Max)
Package Width (mm)
14.2(Max)
Package Height (mm)
1.7(Max)
Seated Plane Height (mm)
2.41(Max)
Pin Pitch (mm)
1.27
Package Material
Plastic
Mounting
Surface Mount
Density
4Mbit
Address Bus Width
18bit
Maximum Access Time
6.5ns
Timing Type
Synchronous
Maximum Clock Rate
133MHz
Data Rate Architecture
SDR
Density in Bits
4194304bit
Maximum Operating Current
175mA
Typical Operating Supply Voltage
2.5V
Number of Bits per Word
18bit
Number of Ports
2
Number of Words
256K
Min Operating Supply Voltage
2.45V
Max Operating Supply Voltage
2.55V
Min Operating Temperature
0°C
Max Operating Temperature
70°C
Architecture
Flow-Through
Compliance
Cage Code
1J9V2
EU RoHS
No
HTS Code
8542320041
Schedule B
8542320040
ECCN
3A991.b.2.a
Automotive
No
AEC Qualified
No
PPAP
No
Radiation Hardening
No
RoHS Versions
2011/65/EU, 2015/863
Datasheet
Integrated Silicon Solution IS61NVF25618A-6.5B2 Datasheet
Download the complete datasheet for Integrated Silicon Solution IS61NVF25618A-6.5B2 to view detailed technical specifications.
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