The Intel 8255A is a general purpose programmable I/O device designed for use with Intel microprocessors. It has 24 I/O pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation. It interfaces peripheral equipment to the microcomputer system bus.
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Intel 8255A technical specifications.
| I/O Pins | 24 |
| Package Type | 40 Pin DIP |
| Package Type Code | P |
| Control Application Interface | Direct Bit Set/Reset Capability |
| System Package Count | Reduced |
| DC Driving Capability | Improved |
| Temperature Range | Standard and Extended |
| Ambient Temperature Under Bias | 0 to 70°C |
| Storage Temperature | -65 to +150°C |
| Voltage on Any Pin with Respect to Ground | -0.5 to +7V |
| Power Dissipation | 1Watt |
| Input Low Voltage (VIL) | -0.5 to 0.8V |
| Input High Voltage (VIH) | 2.0 to VccV |
| Output Low Voltage (Data Bus) (VOL (DB)) | 0.45V |
| Output Low Current (Data Bus) | 2.5mA |
| Output Low Voltage (Peripheral Port) (VOL (PER)) | 0.45V |
| Output Low Current (Peripheral Port) | 1.7mA |
| Output High Voltage (Data Bus) (VOH (DB)) | 2.4V |
| Output High Current (Data Bus) | -400µA |
| Output High Voltage (Peripheral Port) (VOH (PER)) | 2.4V |
| Output High Current (Peripheral Port) | -200µA |
| Darlington Drive Current (IDAR) | -1.0 to -4.0mA |
| Power Supply Current (Icc) | 120mA |
| Input Load Current (IIL) | ±10µA |
| Output Float Leakage (IOFL) | ±10µA |
| Input Capacitance (CIN) | 10pF |
| I/O Capacitance (CI/O) | 20pF |
| Address Stable before READ (tAR) | 0ns |
| Address Stable after READ (tRA) | 0ns |
| READ Pulse Width (tRR) | 300ns |
| Data Valid from READ (tRD) | 8255A: 250, 8255A-5: 200ns |
| Data Float after READ (tDF) | 10 to 150 (8255A), 10 to 100 (8255A-5)ns |
| Time between READs and/or WRITES (tRV) | 850ns |
| Address Stable before WRITE (tAW) | 0ns |
| Address Stable after WRITE (tWA) | 20ns |
| WRITE Pulse Width (tWW) | 8255A: 400, 8255A-5: 300ns |
| Data Valid to WRITE (tDW) | 100ns |
| Data Valid after WRITE (tWD) | 30ns |
| WR = 1 to Output (tWB) | 350ns |
| Peripheral Data before RD (tIR) | 0ns |
| Peripheral Data after RD (tHR) | 0ns |
| ACK Pulse Width (tAK) | 300ns |
| STB Pulse Width (tST) | 500ns |
| Per. Data before T.E. of STB (tPS) | 0ns |
| Per. Data after T.E. of STB (tPH) | 180ns |
| ACK = 0 to Output (tAD) | 300ns |
| ACK = 1 to Output Float (tKD) | 20 to 250ns |
| WR=1 to OBF=0 (tWOB) | 650ns |
| ACK=0 to OBF=1 (tAOB) | 350ns |
| STB=0 to IBF=1 (tSIB) | 300ns |
| RD=1 to IBF=0 (tRIB) | 300ns |
| RD=0 to INTR=0 (tRIT) | 400ns |
| STB=1 to INTR=1 (tSIT) | 300ns |
| ACK=1 to INTR=1 (tAIT) | 350ns |
| WR=0 to INTR=0 (tWIT) | 850ns |
| Pin Name | D7-D0Data Bus (Bi-Directional) |
| Pin Name | RESETReset Input |
| Pin Name | CSChip Select |
| Pin Name | RDRead Input |
| Pin Name | WRWrite Input |
| Pin Name | A0, A1Port Address |
| Pin Name | PA7-PA0Port A (BIT) |
| Pin Name | PB7-PB0Port B (BIT) |
| Pin Name | PC7-PC0Port C (BIT) |
| Pin Name | Vcc+5 Volts |
| Pin Name | GND0 Volts |
| Operating Mode | Mode 0: Basic Input/Output |
| Operating Mode | Mode 1: Strobed Input/Output |
| Operating Mode | Mode 2: Bi-Directional Bus (Strobed Bidirectional Bus I/O) |
| Output Buffer Source Current | 1mA at 1.5 volts (for any 8 output buffers from Ports B and C) |
| Cage Code | 4BA62 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2002/95/EC |
| Compatibility | MCS-85 Compatible |
| Compatibility | TTL Compatible |
| Compatibility | Intel Microprocessor Families |
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