Field-Programmable Gate Array (FPGA) with 4160 logic cells and 263,000 system gates, built on 0.22um process technology. Features 52 Kbit RAM bits, 26 block RAMs, and 2 DLLs/PLLs, supporting up to 246 user I/Os. This surface-mount device utilizes a 356-pin BGA package (35x35x1.1mm) with 1.27mm pin pitch, compatible with LVPECL, LVDS, PCI-X, AGP, CTT, LVTTL, and LVCMOS I/O standards. Offers external memory interface for DDR SDRAM and ZBT SRAM, operating within a 0°C to 85°C temperature range.
PackageBGA
MountingSurface Mount
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Technical Specifications
Intel EP20K100EBC356XNES technical specifications.
General
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | BGA |
| Package Description | Plastic Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 356 |
| PCB | 356 |
| Package Length (mm) | 35 |
| Package Width (mm) | 35 |
| Package Height (mm) | 1.1(Max) |
| Seated Plane Height (mm) | 1.7(Max) |
| Pin Pitch (mm) | 1.27 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Jedec | MO-192BAR-2 |
| Family Name | APEX 20K |
| Maximum Number of User I/Os | 246 |
| RAM Bits | 52Kbit |
| Device Logic Cells | 4160 |
| Process Technology | 0.22um |
| Device System Gates | 263000 |
| Programmability | No |
| Program Memory Type | SRAM |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 85°C |
| Speed Grade | STD |
| Differential I/O Standards Supported | LVPECL|LVDS|PCI-X|AGP|CTT |
| Single-Ended I/O Standards Supported | LVTTL|LVCMOS |
| External Memory Interface | DDR SDRAM|ZBT SRAM |
| Device Number of DLLs/PLLs | 2 |
| Total Number of Block RAM | 26 |
Compliance
| Cage Code | 4BA62 |
| EU RoHS | Yes |
| HTS Code | 8542390001 |
| Schedule B | 8542390000 |
| ECCN | 3A991.d |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2002/95/EC |
Datasheet
Intel EP20K100EBC356XNES Datasheet
Download the complete datasheet for Intel EP20K100EBC356XNES to view detailed technical specifications.
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