Field Programmable Gate Array (FPGA) with 200K system gates and 8320 logic cells. Features 104 Kbit RAM, 52 block RAMs, and 2 DLLs/PLLs. Supports up to 271 user I/Os with differential standards including LVPECL, LVDS, PCI-X, AGP, and CTT, alongside single-ended LVTTL and LVCMOS. Offers external memory interface for DDR SDRAM and ZBT SRAM. Packaged in a 356-pin BGA (35x35x1.1mm) for surface mounting, operating from 0°C to 85°C.
PackageBGA
MountingSurface Mount
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Technical Specifications
Intel EP20K200EBC356NES technical specifications.
General
Basic Package Type
Ball Grid Array
Package Family Name
BGA
Package/Case
BGA
Package Description
Plastic Ball Grid Array
Lead Shape
Ball
Pin Count
356
PCB
356
Package Length (mm)
35
Package Width (mm)
35
Package Height (mm)
1.1(Max)
Seated Plane Height (mm)
1.7(Max)
Pin Pitch (mm)
1.27
Package Material
Plastic
Mounting
Surface Mount
Jedec
MO-192BAR-2
Family Name
APEX 20K
Maximum Number of User I/Os
271
RAM Bits
104Kbit
Device Logic Cells
8320
Process Technology
0.22um
Device System Gates
526000
Programmability
No
Program Memory Type
SRAM
Min Operating Temperature
0°C
Max Operating Temperature
85°C
Speed Grade
STD
Differential I/O Standards Supported
LVPECL|LVDS|PCI-X|AGP|CTT
Single-Ended I/O Standards Supported
LVTTL|LVCMOS
External Memory Interface
DDR SDRAM|ZBT SRAM
Device Number of DLLs/PLLs
2
Total Number of Block RAM
52
Compliance
Cage Code
4BA62
EU RoHS
Yes
HTS Code
8542390001
Schedule B
8542390000
ECCN
3A991.d
Automotive
No
AEC Qualified
No
PPAP
No
Radiation Hardening
No
RoHS Versions
2002/95/EC
Datasheet
Intel EP20K200EBC356NES Datasheet
Download the complete datasheet for Intel EP20K200EBC356NES to view detailed technical specifications.
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