Field Programmable Gate Array (FPGA) with 8320 logic cells and 526,000 system gates, utilizing 0.22um process technology. Features 104 Kbit RAM, 52 block RAMs, and 2 DLLs/PLLs. Supports 376 user I/Os with LVTTL, LVCMOS, LVPECL, LVDS, PCI-X, AGP, and CTT differential standards. Offers external memory interfaces for DDR SDRAM and ZBT SRAM. Packaged in a 484-pin Fine Pitch Ball Grid Array (FBGA) for surface mounting, operating from 0°C to 85°C.
PackageFBGA
MountingSurface Mount
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Technical Specifications
Intel EP20K200EFC484XNES technical specifications.
General
Basic Package Type
Ball Grid Array
Package Family Name
BGA
Package/Case
FBGA
Package Description
Fine Pitch Ball Grid Array
Lead Shape
Ball
Pin Count
484
PCB
484
Package Length (mm)
23
Package Width (mm)
23
Package Height (mm)
2.2(Max)
Seated Plane Height (mm)
2.6(Max)
Pin Pitch (mm)
1
Package Material
Plastic
Mounting
Surface Mount
Jedec
MS-034AAJ-1
Family Name
APEX 20K
Maximum Number of User I/Os
376
RAM Bits
104Kbit
Device Logic Cells
8320
Process Technology
0.22um
Device System Gates
526000
Programmability
No
Program Memory Type
SRAM
Min Operating Temperature
0°C
Max Operating Temperature
85°C
Speed Grade
STD
Differential I/O Standards Supported
LVPECL|LVDS|PCI-X|AGP|CTT
Single-Ended I/O Standards Supported
LVTTL|LVCMOS
External Memory Interface
DDR SDRAM|ZBT SRAM
Device Number of DLLs/PLLs
2
Total Number of Block RAM
52
Compliance
Cage Code
4BA62
EU RoHS
Yes
HTS Code
8542390001
Schedule B
8542390000
ECCN
3A991.d
Automotive
No
AEC Qualified
No
PPAP
No
Radiation Hardening
No
RoHS Versions
2002/95/EC
Datasheet
Intel EP20K200EFC484XNES Datasheet
Download the complete datasheet for Intel EP20K200EFC484XNES to view detailed technical specifications.
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