Field Programmable Gate Array (FPGA) with 728,000 system gates and 11,520 logic cells. Features 144 Kbit RAM, 72 block RAMs, and 4 DLLs/PLLs. Supports 408 maximum user I/Os with LVPECL, LVDS, PCI-X, AGP, CTT, LVTTL, and LVCMOS standards. External memory interface includes DDR SDRAM and ZBT SRAM. Packaged in a 652-pin BGA (45mm x 45mm x 2.8mm) for surface mounting, operating from 0°C to 85°C.
PackageBGA
MountingSurface Mount
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Technical Specifications
Intel EP20K300EBC652XNES technical specifications.
General
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | BGA |
| Package Description | Plastic Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 652 |
| PCB | 652 |
| Package Length (mm) | 45 |
| Package Width (mm) | 45 |
| Package Height (mm) | 2.8(Max) |
| Seated Plane Height (mm) | 3.2(Max) |
| Pin Pitch (mm) | 1.27 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Jedec | MS-034BAW-1 |
| Family Name | APEX 20K |
| Maximum Number of User I/Os | 408 |
| RAM Bits | 144Kbit |
| Device Logic Cells | 11520 |
| Process Technology | 0.22um |
| Device System Gates | 728000 |
| Programmability | No |
| Program Memory Type | SRAM |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 85°C |
| Speed Grade | STD |
| Differential I/O Standards Supported | LVPECL|LVDS|PCI-X|AGP|CTT |
| Single-Ended I/O Standards Supported | LVTTL|LVCMOS |
| External Memory Interface | DDR SDRAM|ZBT SRAM |
| Device Number of DLLs/PLLs | 4 |
| Total Number of Block RAM | 72 |
Compliance
| Cage Code | 4BA62 |
| EU RoHS | Yes |
| HTS Code | 8542390001 |
| Schedule B | 8542390000 |
| ECCN | 3A991.d |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2002/95/EC |
Datasheet
Intel EP20K300EBC652XNES Datasheet
Download the complete datasheet for Intel EP20K300EBC652XNES to view detailed technical specifications.
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