EP20K300EFC672XNES

FPGA APEX 20K, 728K Gates, 11520 Cells, 672-Pin FBGA

Field Programmable Gate Array (FPGA) with 728,000 system gates and 11,520 logic cells. Features 144 Kbit RAM, 72 block RAMs, and 4 DLLs/PLLs. Supports DDR SDRAM and ZBT SRAM external memory interfaces. Offers 408 maximum user I/Os with support for LVPECL, LVDS, PCI-X, AGP, CTT, LVTTL, and LVCMOS standards. Packaged in a 672-pin Fine Pitch Ball Grid Array (FBGA) with a 1mm pin pitch, suitable for surface mounting. Operates within a temperature range of 0°C to 85°C.

PackageFBGA

MountingSurface Mount

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Technical Specifications

Intel EP20K300EFC672XNES technical specifications.

General

Basic Package Type	Ball Grid Array
Package Family Name	BGA
Package/Case	FBGA
Package Description	Fine Pitch Ball Grid Array
Lead Shape	Ball
Pin Count	672
PCB	672
Package Length (mm)	27
Package Width (mm)	27
Package Height (mm)	2.2(Max)
Seated Plane Height (mm)	2.6(Max)
Pin Pitch (mm)	1
Package Material	Plastic
Mounting	Surface Mount
Jedec	MS-034AAL-1
Family Name	APEX 20K
Maximum Number of User I/Os	408
RAM Bits	144Kbit
Device Logic Cells	11520
Process Technology	0.22um
Device System Gates	728000
Programmability	No
Program Memory Type	SRAM
Min Operating Temperature	0°C
Max Operating Temperature	85°C
Speed Grade	STD
Differential I/O Standards Supported	LVPECL\|LVDS\|PCI-X\|AGP\|CTT
Single-Ended I/O Standards Supported	LVTTL\|LVCMOS
External Memory Interface	DDR SDRAM\|ZBT SRAM
Device Number of DLLs/PLLs	4
Total Number of Block RAM	72

Compliance

Cage Code	4BA62
EU RoHS	Yes
HTS Code	8542390001
Schedule B	8542390000
ECCN	3A991.d
Automotive	No
AEC Qualified	No
PPAP	No
Radiation Hardening	No
RoHS Versions	2002/95/EC

Datasheet

This datasheet cannot be embedded due to technical restrictions.

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