
Field Programmable Gate Array (FPGA) with 11,520 logic cells and 728,000 system gates, built on 0.22um process technology. Features 144 Kbit RAM, 72 block RAMs, and 4 DLLs/PLLs. Supports up to 152 user I/Os with differential standards including LVPECL, LVDS, PCI-X, AGP, CTT, and single-ended standards like LVTTL, LVCMOS. Offers external memory interface for DDR SDRAM and ZBT SRAM. Packaged in a 240-pin PQFP (Plastic Quad Flat Package) for surface mounting, with dimensions of 32x32x3.4mm and a 0.5mm pin pitch. Operates within a temperature range of 0°C to 85°C.
Intel EP20K300EQC240XNES technical specifications.
| Basic Package Type | Lead-Frame SMT |
| Package Family Name | QFP |
| Package/Case | PQFP |
| Package Description | Plastic Quad Flat Package |
| Lead Shape | Gull-wing |
| Pin Count | 240 |
| PCB | 240 |
| Package Length (mm) | 32 |
| Package Width (mm) | 32 |
| Package Height (mm) | 3.4 |
| Seated Plane Height (mm) | 4.1(Max) |
| Pin Pitch (mm) | 0.5 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Jedec | MS-029GA |
| Family Name | APEX 20K |
| Maximum Number of User I/Os | 152 |
| RAM Bits | 144Kbit |
| Device Logic Cells | 11520 |
| Process Technology | 0.22um |
| Device System Gates | 728000 |
| Programmability | No |
| Program Memory Type | SRAM |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 85°C |
| Speed Grade | STD |
| Differential I/O Standards Supported | LVPECL|LVDS|PCI-X|AGP|CTT |
| Single-Ended I/O Standards Supported | LVTTL|LVCMOS |
| External Memory Interface | DDR SDRAM|ZBT SRAM |
| Device Number of DLLs/PLLs | 4 |
| Total Number of Block RAM | 72 |
| Cage Code | 4BA62 |
| EU RoHS | Yes |
| HTS Code | 8542390001 |
| Schedule B | 8542390000 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2011/65/EU |
Download the complete datasheet for Intel EP20K300EQC240XNES to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.