Field Programmable Gate Array (FPGA) with 89,178 logic cells and 452 user I/Os, built on 40nm process technology. Features 6.375 Gbps transceiver speed across 12 transceiver blocks and 32 SERDES channels, supporting multiple differential and single-ended I/O standards. Includes 6679 Kbit RAM, 448 18x18 multipliers, 56 dedicated DSP blocks, and 1 Ethernet MAC. Operates within a 0°C to 85°C temperature range, packaged in a 1152-pin, 35x35mm Flip Chip Fine Pitch Ball Grid Array (FC-FBGA) for surface mounting.
PackageFC-FBGA
MountingSurface Mount
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Technical Specifications
Intel EP2AGX95EF35C6NES technical specifications.
General
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | FC-FBGA |
| Package Description | Flip Chip Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 1152 |
| PCB | 1152 |
| Package Length (mm) | 35 |
| Package Width (mm) | 35 |
| Package Height (mm) | 1.9 |
| Seated Plane Height (mm) | 2.4 |
| Pin Pitch (mm) | 1 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Jedec | MS-034AAR-1 |
| Family Name | Arria® II GX |
| Maximum Number of User I/Os | 452 |
| RAM Bits | 6679Kbit |
| Device Logic Cells | 89178 |
| Process Technology | 40nm |
| Ethernet MACs | 1 |
| Number of Multipliers | 448 (18x18) |
| Programmability | Yes |
| Transceiver Blocks | 12 |
| Transceiver Speed | 6.375Gbps |
| Program Memory Type | SRAM |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 85°C |
| Dedicated DSP | 56 |
| PCI Blocks | 1 |
| Maximum Number of SERDES Channels | 32 |
| Speed Grade | 6 |
| Differential I/O Standards Supported | LVPECL|LVDS|HSTL-18|HSTL-15|HSTL-12 |
| Single-Ended I/O Standards Supported | LVTTL|LVCMOS |
| External Memory Interface | DDR SDRAM|DDR2 SDRAM|DDR3 SDRAM|RLDRAM II|QDRII+SRAM |
| Device Number of DLLs/PLLs | 6 |
| Supported IP Core | Video LVDS SerDes Transmitter / Receiver|10/100/1G Ethernet MACController (GMAC)|IP Compiler for PCI Express x8 (Soft IP)|Hashing IP Core (BA413)|10/100/1000Mbps Full Duplex Ethernet MAC |
| Supported IP Core Manufacture | Microtronix Inc/Mobiveil, Inc/CAST, Inc/Barco Silex/MorethanIP |
| Total Number of Block RAM | 612 |
Compliance
| Cage Code | 4BA62 |
| EU RoHS | Yes with Exemption |
| HTS Code | 8542390001 |
| Schedule B | 8542390000 |
| ECCN | 3A991 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2011/65/EU |
Datasheet
Intel EP2AGX95EF35C6NES Datasheet
Download the complete datasheet for Intel EP2AGX95EF35C6NES to view detailed technical specifications.
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