
Field-Programmable Gate Array (FPGA) with 90,960 logic cells and 4.4145 Mbit of RAM. This device features 1152 pins in a 35mm x 35mm Flip Chip Fine Pitch Ball Grid Array (FC-FBGA) package, designed for surface mounting. It operates at a maximum frequency of 732.1MHz using 90nm process technology and supports up to 558 user I/Os. The FPGA includes 12 transceiver blocks capable of 6.375 Gbps and supports various differential and single-ended I/O standards, along with external memory interfaces like DDR2 SDRAM.
Sign in to ask questions about the Intel EP2SGX90EF35C4N datasheet using AI. Get instant answers about specifications, features, and technical details, ideal for finding information in larger documents.
Sign In to ChatWidest selection of semiconductors and electronic components in stock and ready to ship ™
Intel EP2SGX90EF35C4N technical specifications.
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | FC-FBGA |
| Package Description | Flip Chip Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 1152 |
| PCB | 1152 |
| Package Length (mm) | 35 |
| Package Width (mm) | 35 |
| Package Height (mm) | 3(Max) |
| Seated Plane Height (mm) | 3.5(Max) |
| Pin Pitch (mm) | 1 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Jedec | MS-034AAR-1 |
| Family Name | Stratix® II GX |
| Maximum Number of User I/Os | 558 |
| RAM Bits | 4414.5Kbit |
| Device Logic Cells | 90960 |
| Process Technology | 90nm |
| Number of Multipliers | 192 (18x18) |
| Programmability | No |
| Transceiver Blocks | 12 |
| Transceiver Speed | 6.375Gbps |
| Program Memory Type | SRAM |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 85°C |
| Dedicated DSP | 48 |
| Speed Grade | 4 |
| Differential I/O Standards Supported | LVPECL|LVDS |
| Single-Ended I/O Standards Supported | LVTTL|LVCMOS|SSTL|HSTL |
| External Memory Interface | DDR2 SDRAM|RLDRAM II|QDRII+SRAM |
| Device Number of DLLs/PLLs | 8 |
| Supported IP Core | Viterbi Compiler, Low-Speed/Hybrid Serial Decoder|Viterbi Compiler, High-Speed Parallel Decoder|Video LVDS SerDes Transmitter/Receiver|RapidIO to AXI Bridge Controller (RAB)|PowerPC/SH/1960 System Controller |
| Supported IP Core Manufacture | Altera/CAST, Inc/Microtronix Inc/Mobiveil, Inc/Eureka Technology Inc |
| Total Number of Block RAM | 4+408+488 |
| Cage Code | 4BA62 |
| EU RoHS | Yes with Exemption |
| HTS Code | 8542390001 |
| Schedule B | 8542390000 |
| ECCN | 3A991.d |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| RoHS Versions | 2011/65/EU |
Download the complete datasheet for Intel EP2SGX90EF35C4N to view detailed technical specifications.
The embedded preview will load automatically when this section scrolls into view.