
Field Programmable Gate Array (FPGA) with 100,448 logic cells and 483 total block RAM. Features 4,347 Kbit RAM bits and 276 multipliers (18x18). Operates at 437.5MHz with 65nm process technology and a 1.2V supply. Supports a maximum of 413 user I/Os with extensive single-ended and differential I/O standards. Packaged in a 780-pin FBGA (Fine Pitch Ball Grid Array) for surface mounting.
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| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | FBGA |
| Package Description | Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 780 |
| PCB | 780 |
| Package Length (mm) | 29 |
| Package Width (mm) | 29 |
| Package Height (mm) | 1.75 |
| Seated Plane Height (mm) | 2.25 |
| Pin Pitch (mm) | 1 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Jedec | MS-034AAM-1 |
| Family Name | Cyclone® III LS |
| Maximum Number of User I/Os | 413 |
| RAM Bits | 4347Kbit |
| Device Logic Cells | 100448 |
| Process Technology | 65nm |
| Number of Multipliers | 276 (18x18) |
| Programmability | No |
| Program Memory Type | SRAM |
| Min Operating Temperature | -40°C |
| Max Operating Temperature | 100°C |
| Speed Grade | 7 |
| Differential I/O Standards Supported | LVPECL|LVDS|HSTL-18|HSTL-15|HSTL-12|SSTL-2|SSTL-18|RSDS |
| Single-Ended I/O Standards Supported | LVTTL|LVCMOS|PCI|PCI-X|SSTL|HSTL |
| External Memory Interface | DDR2 SDRAM|QDRII+SRAM |
| Device Number of DLLs/PLLs | 4 |
| Supported IP Core | Viterbi Compiler, Low-Speed/Hybrid Serial Decoder|Public Key Crypto Engine (BA414E)| 32|64-bit PCI-X bus Master/Target interface Core, 66/100/133Mhz |
| Supported IP Core Manufacture | Altera/CAST, Inc/Barco Silex/PLDA |
| Total Number of Block RAM | 483 |
| Cage Code | 4BA62 |
| EU RoHS | Yes with Exemption |
| HTS Code | 8542390001 |
| Schedule B | 8542390000 |
| ECCN | 3A991 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2011/65/EU, 2015/863 |
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