
Complex Programmable Logic Device (CPLD) featuring 192 macrocells and 240 logic cells. This device operates at 201.1MHz with 0.18um process technology and a 1.8V supply voltage. It offers 80 user I/Os and is housed in a 100-pin Thin Profile Fine Pitch Ball Grid Array (TFBGA) package for surface mounting. The CPLD supports in-system programmability and operates within a temperature range of -40°C to 100°C.
Intel EPM240GF100I5NES technical specifications.
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