Complex Programmable Logic Device (CPLD) featuring 440 macro cells and 57 logic elements. This device operates at 201.1MHz with 0.18um process technology and supports 2.5V/3.3V supply voltages. It offers 76 user I/Os and is housed in a 100-pin Thin Fine Pitch Ball Grid Array (TFBGA) package for surface mounting. Programmable and in-system programmable, this CPLD is designed for operation between 0°C and 85°C.
PackageTFBGA
MountingSurface Mount
Quick Jump:
Technical Specifications
Intel EPM570F100C5NES technical specifications.
General
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | TFBGA |
| Package Description | Thin Fine Pitch Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 100 |
| PCB | 100 |
| Package Length (mm) | 11 |
| Package Width (mm) | 11 |
| Package Height (mm) | 1 |
| Seated Plane Height (mm) | 1.4 |
| Pin Pitch (mm) | 1 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Jedec | MO-192DAC-1 |
| Family Name | MAX® II |
| Device Logic Cells | 570 |
| RAM Bits | 0Kbit |
| Number of User I/Os | 76 |
| Number of Logic Blocks/Elements | 57 |
| Number of Macro Cells | 440 |
| Program Memory Type | Flash |
| Process Technology | 0.18um |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 85°C |
| Typical Operating Supply Voltage | 2.5|3.3V |
| Min Operating Supply Voltage | 2.375V |
| Programmability | Yes |
| In-System Programmability | Yes |
| Speed Grade | 5 |
Compliance
| Cage Code | 4BA62 |
| EU RoHS | Yes |
| HTS Code | 8542390001 |
| Schedule B | 8542390000 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2002/95/EC |
Datasheet
Intel EPM570F100C5NES Datasheet
Download the complete datasheet for Intel EPM570F100C5NES to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.