256MB SDRAM module, 168-pin UDIMM, operating at 133 MHz with a 3.3V supply. Features 72-bit data bus width, 18 chips organized as 32Mx72, and 16Mx8 chip configuration. Supports ECC with dual ranks and a CAS latency of 3. Package dimensions are 133.5mm (L) x 3.99mm (W) x 35.05mm (H) with a 1.27mm pin pitch.
PackageUDIMM
MountingSocket
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Technical Specifications
Micron MT18LSDT3272AY-133L1 technical specifications.
General
| Basic Package Type | Non-Lead-Frame SMT |
| Package Family Name | DIM |
| Package/Case | UDIMM |
| Package Description | Unbuffered Dual In Line Memory Module |
| Lead Shape | No Lead |
| Pin Count | 168 |
| PCB | 168 |
| Package Length (mm) | 133.5(Max) |
| Package Width (mm) | 3.99(Max) |
| Package Height (mm) | 35.05(Max) |
| Pin Pitch (mm) | 1.27 |
| Mounting | Socket |
| Jedec | MO-161 |
| Main Category | DRAM Module |
| Total Density | 256Mbyte |
| Module Type | 168UDIMM |
| Maximum Access Time | 6|5.4ns |
| Maximum Clock Rate | 133MHz |
| Chip Density | 128Mbit |
| Subcategory | SDRAM |
| Data Bus Width | 72bit |
| Number of Chip per Module | 18 |
| Organization | 32Mx72 |
| Typical Operating Supply Voltage | 3.3V |
| Maximum Operating Current | 1368mA |
| Min Operating Supply Voltage | 3V |
| Max Operating Supply Voltage | 3.6V |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 65°C |
| Chip Configuration | 16Mx8 |
| ECC Support | Yes |
| Number of Ranks | Dual |
| CAS Latency | 3 |
Compliance
| Cage Code | 6Y440 |
| EU RoHS | Yes with Exemption |
| HTS Code | 8473301140 |
| Schedule B | 8473300002 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| RoHS Versions | 2011/65/EU |
Datasheet
Micron MT18LSDT3272AY-133L1 Datasheet
Download the complete datasheet for Micron MT18LSDT3272AY-133L1 to view detailed technical specifications.
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