32-bit ColdFire RISC microcontroller featuring a 66 MHz maximum clock rate and 256KB Flash program memory. This surface-mount device utilizes a 81-pin MAP-BGA package with a 10mm x 10mm footprint and 1mm pin pitch. It offers 32KB RAM, 56 programmable I/Os, and supports I2C, SPI, and UART interfaces. Operating from a 3.3V supply, it functions within a -40°C to 85°C temperature range and includes 8 ADC channels.
PackageMAP-BGA
MountingSurface Mount
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Technical Specifications
NXP MCF5213LCVM66J technical specifications.
General
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | MAP-BGA |
| Lead Shape | Ball |
| Pin Count | 81 |
| PCB | 81 |
| Package Length (mm) | 10 |
| Package Width (mm) | 10 |
| Package Height (mm) | 1.12 |
| Seated Plane Height (mm) | 1.6(Max) |
| Pin Pitch (mm) | 1 |
| Package Weight (g) | 0.2431 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Family Name | MCF521x |
| Data Bus Width | 32bit |
| Instruction Set Architecture | RISC |
| Maximum Clock Rate | 66MHz |
| Maximum CPU Frequency | 66MHz |
| Device Core | ColdFire |
| Program Memory Type | Flash |
| Program Memory Size | 256KB |
| RAM Size | 32KB |
| Number of Programmable I/Os | 56 |
| Core Architecture | ColdFire |
| Programmability | Yes |
| Number of Timers | 1 |
| Interface Type | I2C/SPI/UART |
| CAN | 0 |
| I2C | 1 |
| SPI | 1 |
| Ethernet | 0 |
| UART | 3 |
| USART | 0 |
| USB | 0 |
| I2S | 0 |
| Max Operating Supply Voltage | 3.6V |
| Min Operating Temperature | -40°C |
| Max Operating Temperature | 85°C |
| ADC Channels | 8 |
| Number of ADCs | Single |
Compliance
| Cage Code | H1R01 |
| EU RoHS | Yes |
| HTS Code | 8542310001 |
| Schedule B | 8542310000 |
| ECCN | 3A991.a.2 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2011/65/EU, 2015/863 |
Datasheet
NXP MCF5213LCVM66J Datasheet
Download the complete datasheet for NXP MCF5213LCVM66J to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.