32-bit RISC microcontroller featuring an e200 core, operating at up to 64 MHz. This MCU offers 1.5MB of Flash program memory and 96KB of RAM. It includes 149 programmable I/Os and multiple communication interfaces: 6 CAN, 1 I2C, and 6 SPI. The device is housed in a 176-pin LQFP package with a 0.5mm pin pitch, suitable for surface mounting. Operating voltage ranges from 3.3V to 5.5V, with an extended temperature range of -40°C to 125°C.
PackageLQFP
MountingSurface Mount
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Technical Specifications
NXP MPC5607CEMLUR technical specifications.
General
| Basic Package Type | Lead-Frame SMT |
| Package Family Name | QFP |
| Package/Case | LQFP |
| Package Description | Low Profile Quad Flat Package |
| Lead Shape | Gull-wing |
| Pin Count | 176 |
| PCB | 176 |
| Package Length (mm) | 24 |
| Package Width (mm) | 24 |
| Package Height (mm) | 1.45(Max) |
| Seated Plane Height (mm) | 1.6(Max) |
| Pin Pitch (mm) | 0.5 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Family Name | MPC56xx |
| Data Bus Width | 32bit |
| Instruction Set Architecture | RISC |
| Maximum Clock Rate | 64MHz |
| Maximum CPU Frequency | 64MHz |
| Device Core | e200 |
| Program Memory Type | Flash |
| Program Memory Size | 1.5MB |
| RAM Size | 96KB |
| Number of Programmable I/Os | 149 |
| Core Architecture | e200 |
| Programmability | Yes |
| Number of Timers | 2 |
| Interface Type | CAN/I2C/SCI/SPI |
| CAN | 6 |
| I2C | 1 |
| SPI | 6 |
| Ethernet | 0 |
| UART | 0 |
| USART | 0 |
| USB | 0 |
| I2S | 0 |
| Max Operating Supply Voltage | 3.6|5.5V |
| Min Operating Temperature | -40°C |
| Max Operating Temperature | 125°C |
| ADC Channels | 19/29/19/5 |
| Number of ADCs | Quad |
Compliance
| Cage Code | H1R01 |
| HTS Code | 8542310001 |
| Schedule B | 8542310000 |
| Automotive | Yes |
| AEC Qualified | Yes |
| Radiation Hardening | No |
| RoHS Versions | 2002/95/EC |
Datasheet
NXP MPC5607CEMLUR Datasheet
Download the complete datasheet for NXP MPC5607CEMLUR to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.