32-bit RISC microcontroller featuring an e200 core, 2MB Flash program memory, and 592KB RAM. This surface-mount device operates at up to 116 MHz and supports multiple interfaces including CAN (6 channels), Ethernet (1 channel), I2C (4 channels), and SPI (4 channels). Housed in a 256-pin MAP-BGA package with a 1mm pitch, it measures 17x17x1.16mm and operates from -40°C to 105°C. Includes 68 ADC channels.
PackageMAP-BGA
MountingSurface Mount
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Technical Specifications
NXP PPC5668GF0AVMJJ technical specifications.
General
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | MAP-BGA |
| Package Description | Molded Array Process Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 256 |
| PCB | 256 |
| Package Length (mm) | 17 |
| Package Width (mm) | 17 |
| Package Height (mm) | 1.16 |
| Seated Plane Height (mm) | 1.6(Max) |
| Pin Pitch (mm) | 1 |
| Package Weight (g) | 0.7748 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Family Name | MPC56xx |
| Data Bus Width | 32bit |
| Instruction Set Architecture | RISC |
| Maximum Clock Rate | 116MHz |
| Maximum CPU Frequency | 116MHz |
| Device Core | e200 |
| Program Memory Type | Flash |
| Program Memory Size | 2MB |
| RAM Size | 592KB |
| Core Architecture | e200 |
| Programmability | Yes |
| Number of Timers | 2 |
| Interface Type | CAN/Ethernet/I2C/SCI/SPI |
| CAN | 6 |
| I2C | 4 |
| SPI | 4 |
| Ethernet | 1 |
| UART | 0 |
| USART | 0 |
| USB | 0 |
| I2S | 0 |
| Max Operating Supply Voltage | 5.5V |
| Min Operating Temperature | -40°C |
| Max Operating Temperature | 105°C |
| ADC Channels | 68 |
| Number of ADCs | Single |
Compliance
| Cage Code | H1R01 |
| EU RoHS | Yes |
| HTS Code | 8542310001 |
| Schedule B | 8542310000 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2011/65/EU, 2015/863 |
Datasheet
NXP PPC5668GF0AVMJJ Datasheet
Download the complete datasheet for NXP PPC5668GF0AVMJJ to view detailed technical specifications.
This datasheet cannot be embedded due to technical restrictions.