N-channel enhancement mode power MOSFET, 60V drain-source voltage, 8A continuous drain current. Features a 12-pin Micro Lead Frame Package (MLP EP) with an exposed pad, measuring 5mm x 4.5mm x 0.75mm. Offers low on-resistance of 17.5mOhm at 10V Vgs and a maximum power dissipation of 1900mW. Designed for surface mounting with a 0.8mm pin pitch.
PackageMLP EP
MountingSurface Mount
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Technical Specifications
Onsemi FDMQ86530L technical specifications.
General
| Basic Package Type | Non-Lead-Frame SMT |
| Package Family Name | QFN |
| Package/Case | MLP EP |
| Package Description | Micro Lead Frame Package, Exposed Pad |
| Lead Shape | No Lead |
| Pin Count | 12 |
| PCB | 12 |
| Package Length (mm) | 5 |
| Package Width (mm) | 4.5 |
| Package Height (mm) | 0.75(Max) |
| Seated Plane Height (mm) | 0.8(Max) |
| Pin Pitch (mm) | 0.8 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Configuration | Quad |
| Category | Power MOSFET |
| Channel Mode | Enhancement |
| Channel Type | N |
| Number of Elements per Chip | 4 |
| Maximum Drain Source Voltage | 60V |
| Maximum Gate Source Voltage | ±20V |
| Maximum Continuous Drain Current | 8A |
| Maximum Gate Threshold Voltage | 3V |
| Maximum Drain Source Resistance | 17.5@10VmOhm |
| Typical Gate Charge @ Vgs | [email protected]|20@10VnC |
| Typical Gate Charge @ 10V | 33nC |
| Typical Input Capacitance @ Vds | 1725@30VpF |
| Maximum Power Dissipation | 1900mW |
| Min Operating Temperature | -55°C |
| Max Operating Temperature | 150°C |
Compliance
| Cage Code | 5V1P1 |
| EU RoHS | Yes |
| HTS Code | 8541290095 |
| Schedule B | 8541290080 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| RoHS Versions | 2011/65/EU, 2015/863 |
Datasheet
Onsemi FDMQ86530L Datasheet
Download the complete datasheet for Onsemi FDMQ86530L to view detailed technical specifications.
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