18,874,368-bit DDR SRAM with a 2M x 9 organization, offering a maximum access time of 0.45ns. This parallel interface memory features a pipelined architecture and operates with a nominal supply voltage of 1.8V, ranging from 1.7V to 1.9V. Packaged in a 165-ball low-profile plastic grid array (LBGA) with a 1mm terminal pitch, this CMOS component is designed for surface mounting and has a maximum seated height of 1.46mm. It operates within a commercial temperature range of 0°C to 70°C.
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Technical Specifications
Renesas UPD44164095BF5-E40-EQ3 technical specifications.
General
| Access Time-Max | 0.45ns |
| Additional Feature | PIPELINED ARCHITECTURE |
| Density | 18874368b |
| Height - Seated (Max) | 1.46mm |
| JESD-30 Code | R-PBGA-B165 |
| Length | 15mm |
| Max Operating Temperature | 70°C |
| Memory Type | DDR SRAM |
| Memory Width | 9 |
| Min Operating Temperature | 0°C |
| Number of Functions | 1 |
| Number of Words | 2097152 |
| Number of Words Code | 2M |
| Organization | 2MX9 |
| Package Body Material | Plastic |
| Package Code | LBGA |
| Package Shape | Rectangular |
| Package Style | GRID ARRAY, LOW PROFILEMeter |
| Parallel/Serial | PARALLEL |
| RoHS Compliant | No |
| Supply Voltage-Max (Vsup) | 1.9V |
| Supply Voltage-Min (Vsup) | 1.7V |
| Supply Voltage-Nom (Vsup) | 1.8V |
| Surface Mount | Yes |
| Technology | CMOS |
| Temperature Grade | COMMERCIAL |
| Terminal Form | Ball |
| Terminal Pitch | 1mm |
| Terminal Position | BOTTOM |
| Width | 13mm |
Compliance
| RoHS | Not Compliant |
Datasheet
Renesas UPD44164095BF5-E40-EQ3 Datasheet
Download the complete datasheet for Renesas UPD44164095BF5-E40-EQ3 to view detailed technical specifications.
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