18,874,368-bit DDR SRAM with a 2M x 9 organization, offering a maximum access time of 0.45ns. This parallel interface memory features a pipelined architecture and operates with a nominal supply voltage of 1.8V, ranging from 1.7V to 1.9V. Packaged in a 165-ball low-profile plastic grid array (LBGA) with a 1mm terminal pitch, this CMOS component is designed for surface mounting and has a maximum seated height of 1.46mm. It operates within a commercial temperature range of 0°C to 70°C.
Renesas UPD44164095BF5-E40-EQ3 technical specifications.
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