1Gbit GDDR5 SGRAM DRAM Module, PGA Module, featuring a 32-bit data bus width and 16 chips organized as 32Mx32. Operates at a maximum clock rate of 2500 MHz with a maximum access time of 6 ns. Surface mountable via a 170-pin Ball Grid Array (BGA) package, measuring 14mm x 12mm x 0.75mm with a 0.8mm pin pitch. Utilizes a typical operating supply voltage of 1.5V.
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SK Hynix H5GQ1H24AFR-T2L technical specifications.
| Basic Package Type | Ball Grid Array |
| Package Family Name | BGA |
| Package/Case | BGA |
| Package Description | Plastic Ball Grid Array |
| Lead Shape | Ball |
| Pin Count | 170 |
| PCB | 170 |
| Package Length (mm) | 14 |
| Package Width (mm) | 12 |
| Package Height (mm) | 0.75 |
| Seated Plane Height (mm) | 1.1 |
| Pin Pitch (mm) | 0.8 |
| Package Material | Plastic |
| Mounting | Surface Mount |
| Main Category | DRAM Module |
| Total Density | 1Gbit |
| Module Type | PGA Module |
| Maximum Access Time | 6ns |
| Maximum Clock Rate | 2500MHz |
| Chip Density | 64Mbit |
| Subcategory | GDDR5 SGRAM |
| Data Bus Width | 32bit |
| Number of Chip per Module | 16 |
| Organization | 32Mx32 |
| Chip Package Type | BGA |
| Typical Operating Supply Voltage | 1.5V |
| Maximum Operating Current | 1630mA |
| Min Operating Supply Voltage | 1.455V |
| Max Operating Supply Voltage | 1.545V |
| ECC Support | No |
| Cage Code | 9162F |
| EU RoHS | Yes |
| HTS Code | 8473301140 |
| Schedule B | 8473300002 |
| ECCN | EAR99 |
| Automotive | No |
| AEC Qualified | No |
| PPAP | No |
| Radiation Hardening | No |
| RoHS Versions | 2002/95/EC |
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