Synchronous DRAM module with 512Mbyte total density, organized as 64Mx72. This 168UDIMM features a 72-bit data bus width and 168 pins, operating at a maximum clock rate of 100 MHz with a CAS latency of 3. The module utilizes TSOP-II packaged chips, each with a 256M bit density and 32Mx8 configuration. It operates on a typical supply voltage of 3.3V, with a range of 3V to 3.6V, and is designed for socket mounting. The unbuffered dual in-line memory module has a package length of 133.35mm and a width of 3.81mm (Max), with a height of 34.93mm.
PackageUDIMM
MountingSocket
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Technical Specifications
Unigen UG564S7488KC-PLAT technical specifications.
General
| Basic Package Type | Non-Lead-Frame SMT |
| Package Family Name | DIMM |
| Package/Case | UDIMM |
| Package Description | Unbuffered Dual In Line Memory Module |
| Lead Shape | No Lead |
| Pin Count | 168 |
| PCB | 168 |
| Package Length (mm) | 133.35 |
| Package Width (mm) | 3.81(Max) |
| Package Height (mm) | 34.93 |
| Pin Pitch (mm) | 1.27 |
| Mounting | Socket |
| Main Category | DRAM Module |
| Total Density | 512Mbyte |
| Module Type | 168UDIMM |
| Maximum Clock Rate | 100MHz |
| Chip Density | 256Mbit |
| Subcategory | Synchronous |
| Data Bus Width | 72bit |
| Number of Chip per Module | 18 |
| Organization | 64Mx72 |
| Chip Package Type | TSOP-II |
| Typical Operating Supply Voltage | 3.3V |
| Min Operating Supply Voltage | 3V |
| Max Operating Supply Voltage | 3.6V |
| Min Operating Temperature | 0°C |
| Max Operating Temperature | 70°C |
| Chip Configuration | 32Mx8 |
| ECC Support | No |
| CAS Latency | 3 |
Compliance
| Cage Code | 08DX2 |
| EU RoHS | Yes |
| HTS Code | 8473301140 |
| Schedule B | 8473300002 |
| Radiation Hardening | No |
| RoHS Versions | 2002/95/EC |
Datasheet
Unigen UG564S7488KC-PLAT Datasheet
Download the complete datasheet for Unigen UG564S7488KC-PLAT to view detailed technical specifications.
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