UG564S7488KC-PLAT

Synchronous DRAM module with 512Mbyte total density, organized as 64Mx72. This 168UDIMM features a 72-bit data bus width and 168 pins, operating at a maximum clock rate of 100 MHz with a CAS latency of 3. The module utilizes TSOP-II packaged chips, each with a 256M bit density and 32Mx8 configuration. It operates on a typical supply voltage of 3.3V, with a range of 3V to 3.6V, and is designed for socket mounting. The unbuffered dual in-line memory module has a package length of 133.35mm and a width of 3.81mm (Max), with a height of 34.93mm.