Field Programmable Gate Array, 100MHz, 47500-Cell, CMOS, PBGA484
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Technical Specifications
Altera EP3SL50F484I2N technical specifications.
General
| Number of Terminals | 484 |
| Terminal Position | BOTTOM |
| JEDEC Package Code | S-PBGA-B484 |
| Number of Outputs | 296 |
| Clock Frequency-Max | 100 |
| Number of Inputs | 296 |
Compliance
| RoHS | Yes |
| Lead Free | Yes |
| REACH | Compliant |
| Military Spec | False |
Datasheet
Altera EP3SL50F484I2N Datasheet
Download the complete datasheet for Altera EP3SL50F484I2N to view detailed technical specifications.
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