The 24-bit sigma-delta ADC provides a maximum fully filtered output word rate of 625 kSPS. It combines a fully differential modulator input, on-chip differential amplifier, reference buffer, programmable decimation, and a low-pass FIR filter with default or user-programmable coefficients. The converter supports dynamic range up to 120.5 dB at a 78 kHz output data rate and 109.5 dB at a 625 kHz output data rate. It operates from mixed 2.5 V and 5 V supplies with a 1.65 V to 2.7 V digital I/O drive supply and is specified from -40°C to +85°C in a 64-lead exposed-pad TQFP package.
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| ADC Resolution | 24bit |
| ADC Architecture | Sigma-Delta |
| Maximum Output Data Rate | 625kSPS |
| Dynamic Range at 78 kHz ODR | 120.5 typdB |
| Dynamic Range at 625 kHz ODR | 109.5 typdB |
| SNR at 78 kHz ODR | 112 typdB |
| SNR at 625 kHz ODR | 107 typdB |
| SFDR at 625 kHz ODR | 120 typdBc |
| THD at 625 kHz ODR | -108 typdB |
| Programmable Oversampling Rate | 32 to 256x |
| Differential Input Range with 4.096 V Reference | ±3.25V p-p |
| Reference Input Voltage Maximum | 4.096V |
| Master Clock Frequency | 1 to 40MHz |
| Normal Mode Power Dissipation | 958 maxmW |
| Low Power Mode Power Dissipation | 661 maxmW |
| Standby Mode Power Dissipation | 6.35 maxmW |
| Operating Temperature Range | -40 to +85°C |
| Package | 64-lead TQFP_EP |
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These are design resources that include the Analog Devices AD7762
User guide for the EVAL-AD7760EDZ and EVAL-AD7762EDZ evaluation boards, used to evaluate the AD7760 and AD7762 24-bit Sigma-Delta ADCs with the EVAL-CED1Z controller.
