Monolithic 12-bit analog-to-digital converter operates from a single 3 V analog supply and supports conversion rates up to 80 MSPS. A differential pipelined architecture, sample-and-hold amplifier, and on-chip voltage reference provide no-missing-codes performance over the industrial temperature range. The analog input supports 1 V p-p to 2 V p-p spans with 500 MHz full-power bandwidth. Parallel digital outputs support offset binary or twos complement formats, and the output driver supply accommodates 2.5 V and 3.3 V logic families.
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| Resolution | 12bits |
| Maximum conversion rate | 80MSPS |
| Minimum conversion rate | 1MSPS |
| Analog supply voltage | 2.7 to 3.6V |
| Output driver supply voltage | 2.25 to 3.6V |
| Power consumption at 80 MSPS | 366 typmW |
| Standby power | 1.0 typmW |
| Analog input bandwidth | 500MHz |
| Analog input span | 1 to 2V p-p |
| SNR at 40 MHz input | 70.4 typdB |
| SFDR at 40 MHz input | 87.8 typdBc |
| DNL | ±0.40 typ, ±0.65 maxLSB |
| INL | ±0.35 typ, ±1.20 maxLSB |
| Pipeline latency | 7cycles |
| Aperture jitter | 0.3 typps rms |
| Output propagation delay | 3.5 typns |
| Operating temperature range | -40 to 85°C |
| Digital data format | Offset binary or twos complement |
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