Clock distribution IC provides three independent outputs configurable for LVDS or CMOS logic levels. The device accepts a differential clock input up to 1.6 GHz and supports output rates up to 800 MHz in LVDS mode or 250 MHz in CMOS mode. Each output includes a programmable divider with integer divide ratios from 1 to 32, and one output includes selectable delay adjustment up to 11.6 ns. The device operates from a single 3.3 V supply in a 32-lead LFCSP package over a −40°C to +85°C temperature range.
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| Product function | Clock distribution IC |
| Clock outputs | 3 independent LVDS/CMOS outputs |
| Differential clock input frequency | 0 to 1.6GHz |
| LVDS output frequency | 0 to 800MHz |
| CMOS output frequency | 0 to 250MHz |
| Programmable dividers | 3 |
| Divider ratio range | 1 to 32 |
| Additive output jitter | 300 typicalfs rms |
| Selectable full-scale delay | 1.8, 6.0, 11.6ns |
| Delay fine adjustment steps | 16 |
| Supply voltage | 3.3 ±5%V |
| Operating temperature range | -40 to +85°C |
| LVDS differential output voltage | 250 to 450mV |
| Clock input sensitivity | 150mV p-p |
| Package | 32-lead LFCSP, 5 mm × 5 mm |
| Thermal resistance, junction-to-ambient | 36.6°C/W |
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