
14-output differential clock buffer and driver supporting CMOS, HSTL, LVDS, and LVPECL interfaces. Features a zero-delay PLL architecture with a maximum frequency of 3.1GHz. Operates from a 3.3V supply voltage with a maximum supply current of 75.8mA. Configurable via I2C and SPI interfaces. Packaged in a 72-pin LFCSP EP with dimensions of 10mm x 10mm x 0.95mm.
Analog Devices AD9523-1BCPZ technical specifications.
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