Multiservice clock generator translates between standard network rates using a fractional-N PLL architecture. The device accepts one or two reference inputs and synthesizes one or two output clocks with single-ended or differential input and output operation. Output frequencies extend to 900 MHz in LVPECL or LVDS modes, while CMOS outputs operate to 200 MHz. A 3-wire SPI-compatible interface supports arbitrary rational frequency translation, and pin programming supports preset network frequency combinations. The device operates from a single 3.3 V supply across a −40°C to +85°C temperature range in a 40-lead LFCSP_VQ package.
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| Reference input frequency range | 19 to 806MHz |
| Reference input capacitance | 3pF |
| Reference input resistance | 6kΩ |
| Reference input duty cycle | 40 to 60% |
| Differential reference input voltage swing | 250mV |
| LVPECL output frequency range | 0 to 900MHz |
| LVDS output frequency range | 0 to 900MHz |
| CMOS output frequency range | 0 to 200MHz |
| Jitter generation, 12 kHz to 20 MHz | 1.3 typical at 19.44 MHz input and 622.08 MHz outputps rms |
| Jitter transfer bandwidth | 180 typicalHz |
| Jitter transfer peaking | 0.1 typicaldB |
| Crystal frequency range | 19 to 52MHz |
| Crystal frequency typical | 26MHz |
| Supply voltage | 3.3V |
| Total supply current | 169 typical, 195 maximummA |
| Operating temperature range | -40 to +85°C |
| Package body size | 6 x 6mm |
| Thermal resistance junction-to-ambient | 45 still air°C/W |
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These are design resources that include the Analog Devices AD9551
User guide for the AD9551 evaluation board, covering hardware setup, Windows-based GUI software, and manual configuration of the multiservice clock generator.
