Floating-point DSP microcomputer provides a 32-bit SHARC architecture core with 2 Mbit of on-chip memory. The device supports high-speed signal-processing workloads with a 25 ns instruction cycle, 40 MIPS instruction throughput, and up to 120 MFLOPS peak floating-point performance. Integrated I/O resources include synchronous serial ports, link ports, DMA support, and an external port for memory and host or multiprocessing interfaces. The family datasheet covers standard and low-power variants with commercial and industrial operating-temperature options.
Checking distributor stock and pricing after the page loads.
Sign in to ask questions about the Analog Devices ADSP-21062 datasheet using AI. Get instant answers about specifications, features, and technical details, ideal for finding information in larger documents.
Sign In to ChatWidest selection of semiconductors and electronic components in stock and ready to ship ™
| Processor architecture | SHARC DSP microcomputer |
| Data path width | 32bit |
| Floating-point data width | 32/40bit |
| On-chip memory | 2Mbit |
| Instruction cycle time | 25ns |
| Instruction throughput | 40MIPS |
| Peak floating-point performance | 120MFLOPS |
| Serial ports | 2 synchronous serial ports |
| Link ports | 6 |
| DMA channels | 10 |
| External address space | 4Gbyte |
| Debug interface | JTAG |
Download the complete datasheet for Analog Devices ADSP-21062 to view detailed technical specifications.
The embedded preview will load automatically when this section scrolls into view.
These are design resources that include the Analog Devices ADSP-21062
Technical guide for bootloading procedures on ADSP-2106x SHARC DSPs, covering EPROM, host, and link port methods for system initialization.
