The SHARC processor is a 32-bit and 40-bit floating-point DSP for high-performance audio and general-purpose signal-processing applications. It uses a SIMD computational architecture and operates at up to 400 MHz with peak performance of 2.4 GFLOPS. On-chip memory includes 2 Mbits of SRAM and 6 Mbits of mask-programmable ROM. Integrated peripherals include a digital applications interface, S/PDIF receiver/transmitter, eight serial ports, asynchronous sample-rate converters, SPI, UART, TWI, PWM, and a 32-bit external memory interface. Package options include 256-ball BGA_ED and 208-lead LQFP_EP versions with commercial and industrial temperature-grade ordering options.
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| Processor family | SHARC |
| Core architecture | SIMD |
| Data formats | 32-bit fixed-point; 32-bit/40-bit floating-point |
| Maximum core clock frequency | 400MHz |
| Minimum instruction cycle time | 2.5ns |
| Peak floating-point performance | 2.4GFLOPS |
| On-chip SRAM | 2Mbit |
| On-chip ROM | 6Mbit |
| External memory interface width | 32/16/8bits |
| SDRAM memory bus width | 32/16bits |
| Serial ports | 8 |
| S/PDIF transceiver | 1 |
| Asynchronous sample rate converters | 4 independent SRC units |
| PWM outputs | 16 |
| DMA channels | 34 |
| SPI-compatible ports | 2 |
| UARTs | 2 |
| TWI interface | I2C-standard compliant two-wire interface |
| External I/O supply voltage | 3.13 to 3.47V |
| Package options | 256-ball BGA_ED; 208-lead LQFP_EP |
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These are design resources that include the Analog Devices ADSP-21369
Evaluation system manual for the ADSP-21369 SHARC processor, featuring the AD1835A audio codec, SDRAM, SRAM, and flash memory for audio application development.
