Single-core SHARC+ digital signal processor supports fixed-point and 32-bit, 40-bit, and 64-bit floating-point processing. The processor family operates at up to 1 GHz and integrates up to 640 kB of L1 SRAM with parity and up to 1 MB of L2 SRAM with ECC. External memory support includes a 16-bit DDR3 and DDR3L SDRAM interface on BGA package options. Integrated peripherals include serial audio, I2C, UART, SPI, link ports, S/PDIF, timers, GPIO, DMA, security, and hardware acceleration features. RoHS-compliant package options include 400-ball CSP_BGA and 120-lead LQFP_EP variants.
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| Processor architecture | SHARC+ single core |
| Processor type | Fixed-point and floating-point DSP |
| Maximum core frequency | 1GHz |
| Floating-point support | 32, 40, 64bit |
| Fixed-point support | 32bit |
| L1 SRAM | 640kB |
| L1 memory protection | Parity |
| L2 SRAM | Up to 1MB |
| L2 memory protection | ECC |
| External memory interface | 16bit |
| External memory type | DDR3/DDR3L SDRAM |
| I2C interfaces | 6 |
| UART interfaces | 3 |
| SPI interfaces | 1 SPI, 2 Quad SPI, 1 Octal SPI |
| Link ports | 2 |
| Timers | 10 timers plus 1 counter |
| CSP_BGA package | 400-ball, 17 mm x 17 mm, 0.8 mm pitch |
| LQFP_EP package | 120-lead, 0.4 mm pitch |
| RoHS | Compliant |
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These are design resources that include the Analog Devices ADSP-21566
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