SHARC+ digital signal processor provides a single high-performance floating-point core with up to 800 MHz operation for the ADSP-21567 speed grades. The device integrates 640 KB of L1 SRAM with parity and 512 KB of shared L2 SRAM with ECC protection. It supports 32-bit, 40-bit, and 64-bit floating-point processing, fixed-point operation, a 16-bit DDR3/DDR3L memory controller, and audio-oriented DAI peripherals. The 400-ball CSP_BGA package measures 17 mm by 17 mm with 0.8 mm pitch and is offered in consumer and industrial junction-temperature ranges. RoHS-compliant orderable models and AEC-Q100-qualified automotive models are documented for the family.
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| Core architecture | SHARC+ single core |
| Maximum core clock | 800MHz |
| L1 SRAM | 640KB |
| L2 SRAM | 512KB |
| Floating-point support | 32, 40, 64bits |
| Fixed-point support | 32bits |
| External memory controller | 16 DDR3/DDR3Lbits |
| SPORT interfaces | 8 full SPORT interfaces with TDM and I2S modes |
| S/PDIF interfaces | 2 receive/transmit |
| ASRC pairs | 8 |
| Precision clock generators | 4 |
| I2C interfaces | 6 |
| UART interfaces | 3 |
| Quad SPI interfaces | 2 |
| Octal SPI interfaces | 1 |
| Link ports | 2 |
| General-purpose timers | 10 |
| Housekeeping ADC | 4-channel 12-bit |
| GPIO pins | 40 GPIO plus 28 DAI pins |
| Package size | 17 x 17 x 1.28mm |
| Package pitch | 0.8mm |
| Industrial junction temperature | -40 to +125°C |
| Consumer junction temperature | 0 to +110°C |
| Core supply voltage | 0.95 to 1.05V |
| External I/O supply voltage | 3.13 to 3.47V |
| RoHS | Compliant |
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These are design resources that include the Analog Devices ADSP-21567
This note explains power sequencing for ADSP-2156x processors to mitigate indeterminate I/O voltage glitches during power-up by ramping VDD_REF before VDD_EXT.
