DSP microcomputer is optimized for digital signal processing and high-speed numeric processing applications. It provides 40 MIPS sustained performance with a 25 ns instruction cycle from a 20 MHz crystal at 5.0 V. The device integrates 80 KB of on-chip RAM configured as 16K words of program memory and 16K words of data memory. It includes independent computational units, two data address generators, a program sequencer, a programmable 16-bit interval timer, and 128-lead TQFP or PQFP package options.
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| Processor type | DSP microcomputer |
| Instruction cycle time | 25ns |
| Crystal frequency | 20MHz |
| Supply voltage | 5.0V |
| Sustained performance | 40MIPS |
| On-chip RAM | 80KB |
| Program memory RAM | 16Kwords |
| Data memory RAM | 16Kwords |
| Timer | 16 interval timer with prescalerbit |
| Architecture | 3-bus architecture |
| Computational units | ALU, multiplier/accumulator, barrel shifter |
| Data address generators | 2 independent |
| Package leads | 128leads |
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These are design resources that include the Analog Devices ADSP-2181
Implementation guide for a digital delay demo on the ADSP-2181 EZ-Kit Lite. Describes circular buffer configuration and source code modifications for the AD1847 codec.
A guide to developing C programs for the ADSP-2181 EZ-KIT LITE, featuring a talkthru example using the AD1847 stereo codec and covering interrupt handling and assembly integration.
