The SHARC+ digital signal processor combines a 1000 MHz SHARC+ core with a 1200 MHz Arm Cortex-A55 core for audio and floating-point processing. It includes 2 MB of shared L2 SRAM, 640 kB of SHARC L1 SRAM, Arm L1 and L2 caches, and a 16-bit DDR3/DDR3L external memory interface. The device provides serial audio, Ethernet, CAN, UART, SPI, TWI, MLB, HADC, timer, watchdog, DMA, cryptographic, and safety-oriented support functions. It is supplied in a 17 mm by 17 mm 400-ball BGA_ED package with 0.8 mm pitch and RoHS-compliant construction.
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| Processor family | SHARC |
| SHARC+ core count | 1 |
| SHARC+ core maximum frequency | 1000MHz |
| Arm core | Cortex-A55 |
| Arm core count | 1 |
| Arm core maximum frequency | 1200MHz |
| Arm performance | 3360DMIPS |
| SHARC L1 SRAM | 640kB |
| System L2 SRAM | 2MB |
| Arm L1 instruction cache | 32kB |
| Arm L1 data cache | 32kB |
| Arm L2 cache | 256kB |
| External memory interface | 16-bit DDR3/DDR3L |
| MemDMA channels | 8 |
| SPORT interfaces | 8 |
| S/PDIF receive/transmit interfaces | 2 |
| Operating junction temperature range | -40 to +125 for B-grade orderable variants°C |
| Package ball count | 400 |
| Package size | 17 x 17mm |
| Package pitch | 0.8mm |
| RoHS | Compliant |
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These are design resources that include the Analog Devices ADSP-SC596
An application note providing a methodology and power calculator guide for estimating power consumption in ADSP-SC596 and ADSP-SC598 SHARC+ processors.
